This invention relates to the field of programmable gate arrays that have static RAM which stores programming bits which define the functionality of the field programmable gate array.
In prior art FPGAs which are SRAM based, there are thousands of individual memory bits which define the desired functionality of the device. These bits are loaded one at a time using the word lines and bit lines and addressing circuitry to address each bit. The bit and word lines define an array with the word lines typically running across the entire FPGA in one direction and the bit lines running across the entire FPGA in an orthogonal direction. The individual memory cells in the array are coupled to the word lines and bit lines in the interstices of the matrix defined by the lines. The whole memory array has to be relatively regular. The memory cells contain the control bits to turn switches on and off in the FPGA""s logic blocks to define the configuration and functionality of the logic blocks. Generally, the memory cells need to be close to the logic blocks they control to minimize routing problems. This forces the logic blocks to be fabricated inside the interstices of the array defined by the word and bit lines of the SRAM memory array. This puts a constraint on the layout of the FPGA which can adversely affect the circuit design because of insufficient space and non optimal spacing between different logic blocks that need to communicate data therebetween.
By forcing the logic blocks to be in the interstices of the memory array in prior art FPGAs, it is frequently necessary to run high speed signal lines over the top of memory cells. Although these high speed signal lines are insulated from the memory cell, they still radiate electromagnetic noise. The EMC emissions can cause soft errors by changing the state of data in the memory cells through capacitive coupling of energy from the high speed data signal into the memory cell. While it is not possible to completely eliminate this problem, it can be alleviated through use of the invention.
The purpose of an FPGA is to provide a customizable logic array to the customer. The critical path is in the design of the FPGA and not the design of the SRAM memory which defines the function of the FPGA. Therefore, the restriction in space available and the routing complications that are caused by the need in the prior art to place logic blocks in the interstices of the logic array create problems.
Thus, a need has arisen for an FPGA structure wherein the need for regularity in the array structure is eliminated such that there is no need to place the logic blocks in the interstices of the memory array.
The invention eliminates the need for a regular array of word lines and bit lines running across the FPGA and the need to put the logic blocks into the interstices of the bit line/word line matrix. An FPGA using the configuration memory according to the teachings of the invention will have the memory cells placed close to the switches etc. being controlled. This allows the memory cells to be built small since they do not need a large drive capability, and it also eliminates long routes for control signals from the memory cells to the devices being controlled thereby. This allows a logic designer specifying the function of an FPGA using the teachings of the invention to optimize the critical paths by placement and routing decisions that make the most sense. The memory cells can be placed anywhere in the logic block, but they are usually placed close to the device being controlled. The selection or control lines can be run to the portions of the various logic blocks being controlled. The memory architecture according to the teachings of the invention also reduces the number of high speed data paths that must be routed over memory cells thereby creating the possibility of soft errors.
These advantages are achieved through the use of a memory architecture that eliminates the use of a conventional regular array of bit lines and word lines to load configuration data into the memory cells. The memory configuration will be called a memory byte architecture because each decoder and group of memory cells includes eight memory cells for a string of eight configuration bits. There is nothing critical about the number eight, and other sizes of groupings can also be used.
In the preferred embodiment, each memory byte has a single flip flop or bistable latch for storing one configuration bit to be loaded into one of the eight static RAM latches. A one-of-eight decoder is interposed between the single flip flop and the eight static RAM latches. The purpose of this decoder is to steer the configuration bit in the flip flop to a selectable one of the eight static RAM latches under the influence of addressing signals supplied by a state machine or programmable computer. The state machine or programmable computer controls a sequence of events to load bits into all eight of the eight static RAM latches of each memory byte. The reader should understand that the selection of the number eight for the number of SRAM latches or other types of memory cells in each memory byte of the configuration memory was purely an arbitrary choice and other numbers could also be chosen with a suitable increase in the span of the decoder from one-of-eight to one-of-X where X is the number of memory cells in each memory xe2x80x9cbytexe2x80x9d. Hereafter, the word xe2x80x9cbytexe2x80x9d should be understood as referring to the number X, whatever that number is chosen to be.
The overall memory structure of an FPGA using the teachings of the invention uses a plurality of these memory bytes. It is the eight static RAM latches of each memory byte which store configuration data that generates the logic signals that are coupled to various switches in the logic blocks and define the functionality of the FPGA.
The configuration data stored in the eight static RAM latches of each memory byte is stored in the static RAM latches using a special memory loading technique involving a serpentine shift register. The single flip flop of each memory byte structure is one link in the serpentine chain of flip flops, all flip flops being connected to act as a serial-input, parallel-output shift register. One output of each flip flop is coupled to the data input of the next flip flop in the serpentine chain. The other output of each flip flop is coupled to the data input of the one-of-eight decoder. The address inputs of the decoder are coupled to the state machine. Each decoder of each memory byte is coupled to the same address bits. Each of the one-of-eight decoders has eight individual data outputs which are coupled to the data inputs of the eight static RAM latches.
Loading of configuration data into the eight static RAM latches of each memory byte structure is accomplished as follows. First, the state machine sets the address bits to all zeroes so as to cut off conductivity of all data paths through the decoder. Then the state machine loads the configuration data that is to be stored in all the xe2x80x9cOxe2x80x9d position static RAM latches of all the memory byte structures having their flip flops in the serpentine chain shift register. This data is in serial format and is shifted into the serpentine chain by clocking the flip flops in the chain as many times as there are flip flops in the chain and bits to be stored. After all the bits are loaded, the state machine changes the address bits to cause each decoder to create a conductive path between the data input of the decoder and the data input of the static RAM latch in the xe2x80x9cOxe2x80x9d position. This causes the configuration bit in each flip flop to be loaded into the xe2x80x9cOxe2x80x9d position static RAM latch of each memory byte. Next, the state machine sets the address lines to all zeroes again to close all conductive paths through the decoder, and the configuration bits for the xe2x80x9c1xe2x80x9d position static RAM latches of each memory byte is shifted into the serpentine shift register. After that data is loaded, the state machine changes the address bits to all the decoders to cause them to open a conductive path from the decoder data input to the data input of the xe2x80x9c1xe2x80x9d position static RAM latches of all memory bytes. This causes all the xe2x80x9c1xe2x80x9d position static RAM latches to be loaded. This process is repeated until all the static RAM latches have been loaded.